1. Technical Field
This invention relates to the field of methods for processing semiconductor materials, and in particular to methods for forming self-aligned wells of P and N type semiconductor materials using a single photo-resist masking step.
2. Background Art
Many semiconductor fabrication process employ steps that produce self-aligned wells in which dopant wells having complementary conductivity properties are placed adjacent to each other. For example, the N and P tubs of CMOS devices are often fabricated using a process that produces self aligned wells. The adjacent wells produced by these processes reduce the amount of semiconductor "real estate" occupied by the corresponding device. In addition, the use of self-aligned well processes eliminates the need to mask the semiconductor wafer with a photo-resist for each ion implantation step.
In place of a second photo-resist mask, conventional self-aligned processes employ a thick oxide layer to mask the semiconductor wafer for ion implantation of the second well. Growth of the thick oxide layer requires elevated temperatures which cause unwanted diffusion of implanted species in the semiconductor wafer. In addition, the thick oxide layers disrupt the planarity of the semiconductor wafer.
There is thus a need for low temperature methods for producing self aligned wells in a semiconductor material without disrupting the planarity of the semiconductor material.